1. Field of the Invention
This invention relates to a memory structure, and particularly to a 1-T memory structure capable of performing hidden refresh, and an operating method applied to the structure, which uses a data latch and an electrically parallel path to effectively eliminate data loss in the prior art from the collision of access actions and refresh actions.
2. Description of the Related Art
FIG. 1 is a schematic diagram of a unit of cell of typical 1-Transistor memory. In FIG. 1, a 1-Transistor gate G1T and a capacitor Cap are connected in serial. As shown in FIG. 1, when the 1-T gate G1T is turned on by a gate-controlled signal WL, a data driver (not shown) powers the capacitor Cap through the bitline selection line BL such that the capacitor Cap is charged to a saturation state. The data signal stored in such a 1-T memory formed of FIG. 1 is increasingly lost with passing time. That is, the charge stored in the capacitor Cap is increasingly reduced. Accordingly, a data refresh to such a 1-T memory is necessary. For a 1-T Dynamic Random Access Memory (DRAM), the frequency of data refresh is about once per 64 ms, and the required time for a data refresh is about 80 ns. For a 1-T Static Random Access Memory (DRAM), the frequency of data refresh is about once per 2 ms, and the required time for a data refresh is about 80 ns. Refresh actions of this frequency easily cause the collision between access actions and refresh actions and further increase the complexity of memory operations.
Therefore, an object of the invention is to provide a 1-T memory structure capable of performing hidden refresh and an operating method applied to the structure, which uses a data latch to effectively eliminate data loss in the prior art from the collision of access actions and refresh actions.
A further object of the invention is to provide a 1-T memory structure capable of performing hidden refresh and an operating method applied to the structure, which uses an electrically parallel path with simple algorithm to reduce the operating complexity and effectively solve the aforementioned data loss problems.
To realize the above and other objects, the invention provides a 1-T memory structure capable of performing hidden refresh and an operating method applied to the structure, which uses a data latch and an electrically parallel path to effectively solve the aforementioned data loss problems. The structure includes: a plurality of memory arrays for storing data signal; a plurality of sense amplifiers for amplifying the data signal of the respective memory array and temporarily storing the amplified data signal; a selector for selecting the amplified data signal through a bus based on a cycle-indicative signal; and a shared data latch for receiving and storing the data signal come from the selector. The operating method includes the following steps: determining if the collision between data access and data refresh is addressed in the same memory array; determining the currently operating mode if the collision happens in the same memory array; if on the data access cycle mode, concurrently refreshing a data signal through a respective sense amplifier bank (SAB) and accessing another data signal through a respective shared data latch (SDL); if on the data refresh cycle mode, first storing the data signal to be refreshed in the shared data latch and then restoring the data signal to be refreshed to the original memory array using the cycle-stealing technique after the data access is completed.